H01L21/31138

Element chip isolation method using laser grooving and plasma etching

An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.

ALTERNATING ETCH AND PASSIVATION PROCESS

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl.sub.2 and BCl.sub.3.

Methods For Depositing Blocking Layers On Metal Surfaces

Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

Silicon-Containing Layer-Forming Composition, and Method for Producing Pattern-Equipped Substrate Which Uses Same
20220384182 · 2022-12-01 ·

Provided is a silicon-containing layer forming composition for forming a silicon-containing layer which exhibits an anti-reflective function during exposure in a multilayer resist process and, during dry etching, shows a high etching rate against a plasma of fluorine-based gas and a low etching rate against a plasma of oxygen-based gas. The silicon-containing layer forming composition includes a polysiloxane compound having a structural unit of the formula: [(R.sup.1).sub.bR.sup.2.sub.mSiO.sub.n/2] and a solvent. In the formula, R.sup.1 is a group represented by the following formula:

##STR00001##

(where a is an integer of 1 to 5; and a wavy line means that a line which the wavy line intersects is a bond); R.sup.2 is each independently a hydrogen atom, a C.sub.1-C.sub.3 alkyl group, a phenyl group, a hydroxy group, a C.sub.1-C.sub.3 alkoxy group or a C.sub.1-C.sub.3 fluoroalkyl group; b is an integer of 1 to 3; m is an integer of 0 to 2; n is an integer of 1 to 3; and a relationship of b+m+n=4 is satisfied.

Organic Mandrel Protection Process

Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

SELECTIVE TANTALUM NITRIDE DEPOSITION FOR BARRIER APPLICATIONS

Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. A substrate with a metal surface, a dielectric surface and an aluminum oxide surface has a blocking layer deposited on the metal surface using an alkylsilane.

INTEGRATED CIRCUIT STRUCTURE AND FABRICATION THEREOF

A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.

Plasma processing apparatus, plasma processing method, and element chip manufacturing method

A plasma processing apparatus for plasma processing a substrate held on a conveying carrier, the carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet. The apparatus includes a controller that controls a plasma generator, an electrostatic adsorption mechanism, and a lifting system, to sequentially execute: an adsorption step allowing the substrate to be adsorbed electrostatically to a stage; an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma; a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage; a holding sheet separation step of separating the holding sheet away from the stage; and a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.

DEPOSITION OF ORGANIC FILMS

Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and/or carbon removal, is also disclosed.