Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The semiconductor substrate may define a feature within the semiconductor substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. A bias power may be applied to the substrate support from a bias power source. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a first non-perpendicular angle to the plane of the surface to deposit the material on one or more features on the substrate and form a first overhang; etching the layer of the substrate beneath the features selective to the deposited material to form a first part of a pattern; removing the material from the features; directing the stream of material from the PVD source toward the surface of the substrate at a second non-perpendicular angle to the plane of the surface to deposit the material on the features on the substrate and form a second overhang; and etching the layer of the substrate beneath the features selective to the deposited material to form a second part of the pattern.

A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

An array substrate and a manufacturing method thereof in the embodiment of the present invention can complete the process of the array substrate with the touch function by using six photolithography processes, thereby simplifying the production process, saving cost, and shortening the production cycle.

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a first non-perpendicular angle to the plane of the surface to deposit the material on one or more features on the substrate and form a first overhang; etching the layer of the substrate beneath the features selective to the deposited material to form a first part of a pattern; removing the material from the features; directing the stream of material from the PVD source toward the surface of the substrate at a second non-perpendicular angle to the plane of the surface to deposit the material on the features on the substrate and form a second overhang; and etching the layer of the substrate beneath the features selective to the deposited material to form a second part of the pattern.

A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having width a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

This application discloses a method for manufacturing an array substrate. The array substrate manufacturing method includes: providing a first substrate; forming gate layers on the first substrate; forming a gate insulation layer on the first substrate, and covering the gate layers; forming an amorphous silicon layer on the gate insulation layer; forming a metal layer on the amorphous silicon layer; forming a photo-sensitive photoresist layer on the metal layer; etching the amorphous silicon layer by using inert gas or nitrogen plasma, to form a groove; forming source layers and a drain layer; removing the photo-sensitive photoresist layer; and forming a passivation layer on the source layers, where a baking process is performed on the photo-sensitive photoresist layer, so that the photo-sensitive photoresist layer flows to some extent so as to form a protection layer, so as to cover the metal layer in a non-active switch channel region.

A method for manufacturing a mold or an optical element provided with a fine surface roughness for anti-reflection or for diffusing, may include placing a substrate or a film made of a semiconductor or a metal into a reacting etching apparatus, introducing a mixed gas of sulfur hexafluoride and oxygen into the etching apparatus with the substrate or the film, tuning the mixed gas into plasma such that oxides are made to be scattered on a surface of the substrate or the film, and etching the surface of the substrate of the film by the sulfur hexafluoride while the oxides function as an etching mask to form the fine surface roughness on the surface of the substrate or the film. Further, etching conditions may be determined such that the pitch of the fine surface roughness is made from 3 to 18 micrometers.

Methods of patterning an amorphous semiconductor layer according to a predetermined pattern via laser ablation with a pulsed laser having a laser wavelength are disclosed. In one aspect, a method may include providing the amorphous semiconductor layer on a substrate, providing a distributed Bragg reflector on the amorphous semiconductor layer, wherein the distributed Bragg reflector is reflective at the laser wavelength, providing an absorbing layer on the distributed Bragg reflector, wherein the absorbing layer is absorptive at the laser wavelength, patterning the absorbing layer by laser ablation, in accordance with the predetermined pattern, patterning the distributed Bragg reflector by performing an etching step using the patterned absorbing layer as an etch mask, and etching the amorphous semiconductor layer using the patterned distributed Bragg reflector as an etch mask. Methods of fabricating silicon heterojunction back contact photovoltaic cell(s) using such amorphous semiconductor layer patterning process are also disclosed.