A method of manufacturing a semiconductor device includes forming a semiconductor layer on an upper surface of a substrate, forming an etching stopper on an upper surface of the semiconductor layer, forming a metal mask including a seed film and a plating film on a lower surface of the substrate, the metal mas having an opening inside the etching stopper in plan view, forming a through-hole in the substrate and the semiconductor layer from the lower surface of the substrate to the etching stopper through the opening, and removing the plating film by an anodic reaction in an electrolyte solution after forming the through-hole.

Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

An interconnect structure for insertion loss reduction in signal transmission and a method thereof are disclosed. In an embodiment, an interconnect is formed on a substrate by chemical etching process, and when the interconnect is protected by photoresist in chemical etching process, the etching direction of etching solution is not oriented, so undercut areas are respectively formed on both sides of a bottom of the interconnect at contact of the interconnect and the substrate because of etching solution residue after the etching process. An included angle formed in the undercut area between the interconnect and the substrate is defined as an etch angle, and a length of the portion, exposing in the undercut area, of the substrate is defined as an etch length. Controlling sizes of the etch angle and the etch length can reduce an insertion loss in signal transmission.

Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

A method for selective etching Si in the presence of silicon nitride and an etching composition with high Si/Si3N4 etching selectivity are disclosed. Particularly, the method for selective etching Si in the presence of silicon nitride is to apply the etching composition with high Si/Si3N4 etching selectivity in the etching process, and the etching composition with high Si/Si3N4 etching selectivity comprises about 0.5 wt. % to about 10 wt. % of at least one quaternary ammonium compound, about 5 wt. % to about 55 wt. % of at least one primary amine, about 15 wt. % to about 80 wt. % of at least one polyol, and about 10 wt. % to about 35 wt. % water based on total weight of the etching composition.

Provided is a treatment liquid for a semiconductor with ruthenium including a ligand which coordinates to ruthenium, the treatment liquid is a treatment liquid for inhibiting a ruthenium-containing gas generated when contacting a semiconductor wafer including ruthenium with the treatment liquid in a semiconductor forming process. Also provided is an inhibitor for the generation of a ruthenium-containing gas, including a compound having a carbonyl group or a heterocyclic compound. Further provided is a treatment agent for a ruthenium-containing waste liquid, including a compound having a carbonyl group or a heterocyclic compound.

The present invention is a sacrificial-film removal method of removing a sacrificial film from a surface of a substrate provided with a plurality of struts and the sacrificial film embedded between the plurality of struts, including: a wet etching step where the sacrificial film is removed to its halfway depth by supplying an etchant to the surface of the substrate; a rinse step where a residue adhering to the surface of the substrate is washed out by supplying a rinsing liquid to the surface of the substrate after the wet etching step; a drying step where a liquid component on the surface of the substrate is removed after the rinse step; and a dry etching step where the sacrificial film remaining on the surface of the substrate is removed by supplying an etching gas to the surface of the substrate after the drying step.

A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers.