An apparatus for perform metal etching and plasma ashing includes: a processing chamber having an enclosed area; an electrostatic chuck disposed in the enclosed area and configured to secure a wafer, the electrostatic chuck connected with a bias power; at least one coil connected with a source power; a etchant conduit configured provide an etchant to a metal of the wafer within the processing chamber in accordance with a photoresist mask of the wafer; and a gas intake conduit connected with a gas source, wherein the gas intake conduit is configured to supply the processing chamber with a gas from the gas source during performance of plasma ashing within the processing chamber.

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Provided are a method of selectively etching a film primarily containing Si, such as polycrystalline silicon (Poly-Si), single crystal silicon (single crystal Si), or amorphous silicon (a-Si) as well as a method for cleaning by removing a Si-based deposited and/or attached matter inside a sample chamber of a film forming apparatus, such as a chemical vapor deposition (CVD) apparatus, without damaging the apparatus interior.

By simultaneously introducing a monofluoro interhalogen gas (XF, where X is any of Cl, Br, and I) and nitric oxide (NO) into an etching or a film forming apparatus, followed by thermal excitation, it is possible to selectively and rapidly etch a Si-based film, such as Poly-Si, single crystal Si, or a-Si, while decreasing the etching rate of SiN and/or SiO.sub.2. It is also possible to perform cleaning by removing a Si-based deposited and/or attached matter inside a film forming apparatus, such as a CVD apparatus, without damaging the apparatus interior.

In one exemplary embodiment, a method for forming a pattern includes (a) forming, on a substrate, a first pattern having an opening and containing a first material, (b) forming a filling portion in the opening, the filling portion containing a second material different from the first material, and (c) removing the first pattern so that the filling portion remains as a second pattern inverted with respect to the first pattern. At least one of the first material or the second material contains tin.

A film forming method includes: preparing a substrate having a recess within a processing container; forming a silicon-containing film on the substrate by activating a silicon-containing gas with plasma and supplying the activated silicon-containing gas to the substrate; partially modifying the silicon-containing film after the silicon-containing film closes an opening of the recess; and selectively etching the modified silicon-containing film.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

A device includes a semiconductive substrate, a semiconductive fin, a stop layer, a fin isolation structure, and a spacer. The semiconductive fin is over the substrate. The stop layer is between the semiconductive substrate and the semiconductive fin. The fin isolation structure is in contact with the semiconductor fin and over the stop layer. A topmost surface of the fin isolation structure is higher than a topmost surface of the semiconductive fin. The spacer at least partially extends along a sidewall of the fin isolation structure.

Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.

A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.