According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

The dry etching method of the present invention etches a metal film formed on a surface of a workpiece by bringing etching gases each containing a β-diketone into contact with the metal film. The method includes: a first etching step of bringing a first etching gas containing a first β-diketone into contact with the metal film; and a second etching step of bringing a second etching gas containing a second β-diketone into contact with the metal film after the first etching step. The first β-diketone is a compound capable of forming a first complex through a reaction with the metal film. The second β-diketone is a compound capable of forming a second complex having a lower sublimation point than the first complex through a reaction with the metal film.

A dry etching method which includes a dry etching step in which an etching gas containing a halogen fluoride being a compound of bromine or iodine and fluorine is brought into contact with a member to be etched (12) including an etching target being a target of etching with the etching gas to etch the etching target without using plasma. The etching target contains copper. Additionally, the dry etching step is performed under temperature conditions of from 140° C. to 300° C. Also disclosed is a method for manufacturing a semiconductor element and a cleaning method using the dry etching method.

A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Semiconductor device is provided. The semiconductor device includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

The present invention is a sacrificial-film removal method of removing a sacrificial film from a surface of a substrate provided with a plurality of struts and the sacrificial film embedded between the plurality of struts, including: a wet etching step where the sacrificial film is removed to its halfway depth by supplying an etchant to the surface of the substrate; a rinse step where a residue adhering to the surface of the substrate is washed out by supplying a rinsing liquid to the surface of the substrate after the wet etching step; a drying step where a liquid component on the surface of the substrate is removed after the rinse step; and a dry etching step where the sacrificial film remaining on the surface of the substrate is removed by supplying an etching gas to the surface of the substrate after the drying step.

The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. The invention provides a solid substrate obtained according to any of the methods of the invention. The invention further provides a porous substrate obtained according to any of the methods of the invention. The invention further provides a patterned solid substrate obtained according to any of the methods of the invention.