A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the N-type region opening, and along a direction perpendicular to the extending direction of the N-type region opening, the width of the first gate structure is larger than the width of the second gate structure.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.

In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure over a substrate. The method includes forming a dielectric layer over the substrate and the first fin structure. The dielectric layer has a first trench exposing a first portion of the first fin structure. The method includes forming a first work function layer in the first trench. The method includes forming a first mask layer over the first work function layer in the first trench, wherein an upper portion of the first work function layer in the first trench is exposed by the first mask layer. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.