A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

A method of microfabrication includes forming an initial stack of semiconductor layers by epitaxial growth over a substrate. The initial stack of semiconductor layers is surrounded by a sidewall structure. The initial stack of semiconductor layers includes channel structures and sacrificial gate layers stacked alternatingly in a vertical direction substantially perpendicular to a working surface of the substrate. The channel structures include a first channel structure and a second channel structure positioned above the first channel structure. First portions of the sidewall structure are removed to uncover first sides of the initial stack. Source/drain (S/D) regions are formed on uncovered side surfaces of the channel structures from the first sides of the initial stack. Second portions of the sidewall structure are removed to uncover second sides of the initial stack. The sacrificial gate layers are replaced with gate structures from the second sides of the initial stack.

The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.

A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.

The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.