A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.

A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

An integrated circuit semiconductor element includes: a substrate; a complementary field effect transistor (FET) (cFET) formed over the substrate and having a quadruple-gate structure, in which nano sheet stacked structures are sequentially stacked; and a planar FET having a mono-gate structure or a zebra fin FET (ZE FINFET) having a triple-gate structure, which are formed over the substrate.

Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.

A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

An integrated circuit semiconductor device includes a first region including first active fins extending in a first direction, and first transistors including first gate electrodes extending in a second direction, a second region in contact with the first region in the second direction, wherein the second region includes second active fins extending in the first direction, and second transistors including second gate electrodes extending in the second direction. The integrated circuit semiconductor device includes metal dams at a boundary of the first region and the second region to separate the first gate electrodes and the second gate electrodes in the second direction, wherein the metal dams, the first gate electrodes, and the second gate electrodes are electrically connected in the second direction.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.