An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.

A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.