Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

A semiconductor package includes a package substrate, an integrated interconnect structure, an optical engine module, and an integrated circuit package. The integrated interconnect structure is bonded over the package substrate and includes an insulation body, a plurality of through vias extending through the insulation body. The optical engine module includes an electronic die, a photonic die, and a waveguide. A portion of the optical engine module is embedded in the integrated interconnect structure. The integrated circuit package is bonded over the integrated interconnect structure and electrically coupled to the optical engine module.

In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.

A package structure is provided. The package structure includes a lower substrate, an upper substrate, and a chip. The lower substrate defines a lower through hole. The upper substrate is over the lower substrate and defines an upper through hole connected to the lower through hole. A portion of a top surface of the lower substrate is exposed by the upper through hole. The chip is at least partially accommodated by the upper through hole and supported by the portion of the top surface of the lower substrate.

Aspects disclosed include an integrated circuit (IC) package with die interconnects of a semiconductor die terminating at multiple metallization layers in a substrate to reduce spacing requirement between die interconnects. The die comprises a first plurality of die interconnects and a second plurality of die interconnects. The substrate includes a first metallization layer adjacent to the die and a second metallization layer that is parallel to the first metallization layer such that the first metallization layer is between the die and second metallization layer. The first and second metallization layers each comprise a respective first plurality of metal pads and a second plurality of metal pads. The first plurality of die interconnects terminates to the first plurality of metal pads in the first metallization layer while the second plurality of die interconnects terminates to the second plurality of metal pads in the second metallization layer.

Unit transistors are provided on a semiconductor substrate and connected in parallel to one another. Capacitors are respectively connected to gate electrodes of the unit transistors. Resistors are respectively connected to the capacitors in parallel. First and second pads are provided on an upper surface of the semiconductor substrate and respectively connected to one end and the other end of the resistor connected to at least the unit transistor in the center among the unit transistors arranged in a row. First and second conductors are provided on a silicon substrate arranged above the semiconductor substrate. A first bump connects the first pad and one end of the first conductor. A second bump connects the second pad and one end of the second conductor. The other ends of the first and second conductors are set in contact with the silicon substrate and are separated from and face each other.

A method of forming a package assembly includes the following operations. At least one integrated circuit structure is bonded to an interposer structure. A photonic structure is bonded to the interposer structure aside the at least one integrated circuit structure. A glass substrate is assembled to a fiber array unit. The glass substrate with the fiber array unit is bonded to the photonic structure. A laser writing process is performed to the glass substrate, so as to form a laser written waveguide structure inside the glass substrate, wherein the laser written waveguide structure is optically coupled to the fiber array unit and the photonic structure.