A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

A semiconductor device can comprise a substrate dielectric structure and a substrate conductive structure that traverses the substrate dielectric structure and comprises first and second substrate terminals; an electronic component with a component terminal coupled to the first substrate terminal; and a first antenna element with a first element terminal coupled to the second substrate terminal, a first element head side adjacent a first antenna pattern, a first element base side opposite the first element side, and a first element sidewall. The first element terminal can be exposed from the first element dielectric structure at the first element base side or at the first element sidewall. The first antenna pattern can be coupled to the substrate through the first element terminal. The substrate conductive structure can couple the first antenna element to the electronic component. Other examples and methods are also disclosed.

A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

A semiconductor device can comprise a substrate dielectric structure and a substrate conductive structure that traverses the substrate dielectric structure and comprises first and second substrate terminals; an electronic component with a component terminal coupled to the first substrate terminal; and a first antenna element with a first element terminal coupled to the second substrate terminal, a first element head side adjacent a first antenna pattern, a first element base side opposite the first element side, and a first element sidewall. The first element terminal can be exposed from the first element dielectric structure at the first element base side or at the first element sidewall. The first antenna pattern can be coupled to the substrate through the first element terminal. The substrate conductive structure can couple the first antenna element to the electronic component. Other examples and methods are also disclosed.

A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.