A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

Semiconductor packages are provided. In one example, a power semiconductor package includes a first carrier submount, a second carrier submount, and a plurality of semiconductor die. Each semiconductor die of the plurality of semiconductor die has a first surface and an opposing second surface. Furthermore, for each semiconductor die of the plurality of semiconductor die, the first surface is directly coupled to the first carrier submount, and the second surface is directly coupled to the second carrier submount.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A wireless transistor outline (TO) package structure includes a carrying module, a chip and a lead frame both mounted on the carrying module, a sheet-like bonding module mounted on the chip and the lead frame in a flip chip manner, and an encapsulant that covers the above components therein. A connection pad of the chip and a connection segment of the lead frame are coplanar with each other. The sheet-like bonding module includes a ceramic substrate and a plurality of circuit layers that are stacked and formed on the ceramic substrate in a direct plated copper (DPC) manner. Areas of the circuit layers gradually decrease in a direction away from the ceramic substrate, and thicknesses of the circuit layers gradually increase in the same direction. The circuit layer arranged away from the ceramic substrate connects the connection pad and the connection segment for establishing an electrical connection therebetween.

A semiconductor device includes a substrate, plugs and a storage node pad structure. The plugs are disposed on the substrate and include first plugs with a conductive material and second plugs with an insulating material. The storage node pad structure is disposed on the plugs and includes first extension pads and at least one second extension pad. The first extension pads have a predetermined first length in a first direction and are separated from each other and arranged as an array along the first direction, being in physical contact with one of the first plugs. The at least one second extension pad has a length greater than the predetermined first length and is in physical contact with at least one of the plugs.

A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

Disclosed are a semiconductor package made from the first and second panel-level methods with at least one pre-made conductive unit. The semiconductor package includes one or more semiconductor dies, a molding layer for encapsulating the one or more semiconductor dies; at least one pre-made conductive unit prepared from a molded conductive substrate; a front build-up layer electrically coupled to the semiconductor dies and the at least one pre-made conductive unit; and an external connection layer electrically coupled to the front build-up layer. The semiconductor dies and pre-made conductive unit may be arranged in either a side-by-side configuration or a vertical configuration. The present application further discloses panel-level methods of making the semiconductor package with the at least one pre-made conductive unit. The present application further relates to several methods of preparing the at least one pre-made conductive unit.

Disclosed are a semiconductor device including highly integrated memory cells, and a method for fabricating the semiconductor device. A semiconductor device includes a memory cell array disposed over the peripheral circuit region; a dummy region including a dummy stack that is spaced apart horizontally from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and dummy region; a stack level plug passing through the dummy stack; and a stack level spacer formed on a sidewall of the stack level plug.