Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 m.

A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 m.

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

A semiconductor package may include a package substrate having a first surface and a second surface, which are opposite to each other, and including a trench formed in the first surface, a substrate pad provided on the package substrate to cover a bottom surface of the trench, a conductive coupling pattern in contact with a top surface of the substrate pad, an anisotropic conductive pattern provided on the conductive coupling pattern and the substrate pad to fill the trench, the anisotropic conductive pattern including conductive capsules and a polymer layer enclosing the conductive capsules, a semiconductor chip mounted on the first surface of the package substrate, and a coupling pillar pattern provided between the package substrate and the semiconductor chip and connected to the conductive coupling pattern in the trench. A top surface of the anisotropic conductive pattern may be coplanar with the first surface of the package substrate.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.