An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

A printed circuit board includes a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first externally exposed surface disposed at substantially the same level as the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to be in contact with a second externally exposed surface of the external connection pad opposing the first externally exposed surface.

A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.

A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

A semiconductor package includes: a package substrate including a plurality of insulating layers and a plurality of metal pattern layers respectively disposed on the plurality of insulating layers, wherein each of the plurality of metal pattern layers has an interconnection layer; at least one semiconductor chip disposed on an upper surface of the package substrate, and connected to the interconnection layer; contact pads disposed on a lower surface of the package substrate, and connected to the interconnection layer; and non-contact pads disposed on the lower surface of the package substrate, and insulated from the interconnection layer, wherein a lowermost metal pattern layer among the plurality of metal pattern layers has a first open region at least partially overlapping at least one non-contact pad among the non-contact pads, in a direction perpendicular to the upper surface of the package substrate.

A semiconductor package includes a first sub-semiconductor package, an interposer substrate, and a second sub-semiconductor package that are sequentially stacked. The first sub-semiconductor package includes a first package substrate, a first semiconductor device, and a first mold member that are sequentially stacked, and the interposer substrate includes at least one hole. The first mold member includes: a mold main portion which covers the first semiconductor device; a mold connecting portion extended from the mold main portion and inserted into the at least one hole; and a mold protruding portion extended from the mold connecting portion to cover a top surface of the interposer substrate outside the at least one hole. The mold main portion, the mold connecting portion, and the mold protruding portion constitute a single object.

A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.