A semiconductor device includes a first semiconductor chip including a conductive pad, an insulating layer provided on the conductive pad, and having an aperture exposing a part of the conductive pad, and a first bump layer provided on the insulating layer and connected to the conductive pad via the aperture, and a second semiconductor chip including an electrode and a second bump layer provided on the electrode. The first bump layer includes a recessed portion provided at the aperture and in contact with the second bump layer, and a raised portion provided adjacent the aperture and in contact with the second bump layer.

A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

The present disclosure relates to an imaging element package, a method of manufacturing the same, and an electronic device capable of further improving reliability. An imaging element package includes a solid-state imaging element having a first pad, a substrate on which the solid-state imaging element is mounted, the substrate having a second pad, and a wire wiring that connects the first pad and the second pad. The wire wiring has a ball portion bonded to the first pad in a shape having a thickness equal to or larger than a depth of an opening portion provided for opening the first pad, and a crescent portion provided by pressing an end of the metal wire against the ball portion and bonding the end to the ball portion, and connected to the metal wire with a connection length of a predetermined ratio or more with respect to the metal wire.

A package structure and a manufacturing method thereof are provided. The package structure includes a substrate having a first surface and a second surface opposite to each other, a die electrically coupled to the substrate, an encapsulant disposed over the first surface of the substrate to encapsulate the die, at least one first conductive terminal and at least one second conductive terminal. The at least one first conductive terminal and the at least one second conductive terminal are disposed on the second surface of the substrate. The at least one second conductive terminal is electrically connected to the die through the substrate. The at least one first conductive terminal is overlapped with the die in a direction perpendicular to the second surface of the substrate. A first area of the at least one first conductive terminal is larger than a second area of the at least one second conductive terminal.

Disclosed herein is a sensor package substrate that includes a first mounting area for mounting a sensor chip. The sensor package substrate has a through hole formed at a position overlapping the first mounting area in a plan view so as to penetrate the sensor package substrate from one surface to the other surface. The through hole includes a first section having a first diameter and a second section having a second diameter smaller than the first diameter. A step part inside the through hole positioned at a boundary between the first and second sections constitutes a second mounting area for mounting an anti-dust filter.

A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

According to one embodiment, a semiconductor device includes a wiring board having a first surface. A first element is disposed on the first surface of the wiring board. A first resin layer covers the first element. A second element is larger than the first element and disposed on the first resin layer. The second element is superposed above the first element. A reinforcement member is disposed at a peripheral portion of the first resin layer and includes an edge disposed inside of the first resin layer. The reinforcement member has an upper surface above the first surface of the wiring board. The reinforcement member has a coefficient of linear expansion lower than the first resin layer. An encapsulating resin material, over the first surface of the wiring board, covers the first element, the second element, the first resin layer, and the reinforcement member.