Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.

A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.

A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

A semiconductor package includes: a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.

A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

A semiconductor package includes: a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

A semiconductor package includes a package substrate including a substrate body having a lower surface and a upper surface, a lower wiring layer on the lower surface and including a land region, an upper wiring layer on the upper surface and electrically connected to the lower wiring layer, and a solder resist layer on the lower surface and including an opening exposing the land region. The semiconductor package further includes a semiconductor chip on the package substrate and having contact pads electrically connected to the upper wiring layer, and a mold part on the package substrate, wherein the package substrate further includes an open region defined by a portion of a bottom surface of the package substrate on which the solder resist layer is not present and that is adjacent to at least one edge of the package substrate on the bottom surface of the package substrate.

The invention relates to a method for producing a module having an electronic chip including metallisations which are accessible from a first side of the metallisations and an integrated circuit chip which is arranged on the second side of the metallisations, opposite the first side. The method comprises the step of forming electrical interconnection elements which are separate from the metallisations, directly connecting the chip, and are arranged on the second side of the metallisations. The invention also relates to a module corresponding to the method and to a device comprising said module.

A sensor package structure is provided and includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped support disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped support. A top portion of the sensor chip defines a sensing region and a carrying region that surrounds the sensing region and that carries the ring-shaped support. The top portion of the sensor chip includes a passivation layer arranged in the sensing region and the carrying region, a color filter arranged in the sensing region and the carrying region, a pixel layer arranged in the sensing region and formed on the central segment, and a micro-lens layer that is formed on the pixel layer. A part of the color filter layer in the carrying region has a roughened surface and at least partially embedded in the ring-shaped support.