An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.

An Integrated Circuit (IC) package has a ferrite-dielectric shield between planar transformer coils and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in transformer coils from reaching the semiconductor chip. Multiple layers of planar transformer coils serve as primary or secondary coils and can be connected together in series or parallel using center posts and coil extensions from outer coil windings to lead-frame risers that also have external package connectors such as pins or bonding balls. The center winding of an upper transformer coil connects to the semiconductor chip on a die attach pad through a center post that fits through an opening in the shield that is over the air core center of the transformer coil. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors.

An electrical circuit in a semiconductor package may include a wire connected at each end by a bond point formed using a wire-bonding machine. When a connection point (e.g., a die pad) has a very small dimension, the wire used for the circuit may be required to have a similarly small diameter. This small diameter can lead to a weak bond point, especially in bonds that include a heel portion. The heel portion is a transition region of the bond point that may have less strength (e.g., as measure by a pull-test) than other portions of the bond point and/or may be exposed to more forces than other portions of the bond point. Accordingly, a capping-bond point may be applied to the bond point to strengthen the bond point by clamping the heel portion and shielding it from forces that could cause cracks.

A transistor outline housing is provided that includes a header for an optoelectronic component. The header has electrical feedthroughs in the form of connection pins embedded in a potting compound. The header has a recess in which at least one of the connection pins in one of the feedthroughs extends out of the lower surface of the header.

A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

A multi-wavelength integrated device (5) including plural semiconductor lasers (6) and plural modulators (7) modulating output beams of the plural semiconductor lasers (6) respectively is mounted on the stem (1). Plural leads (10) penetrates through the stem (1) and are connected to the plural semiconductor lasers (6) and the plural modulators (7) respectively. Each lead (10) is a coaxial line in which plural layers are concentrically overlapped with one another. The coaxial line includes a high frequency signal line (12) transmitting a high frequency signal to the modulator (7), a GND line (14), and a feed line (16) feeding a DC current to the semiconductor laser (6). The high frequency signal line (12) is arranged at a center of the coaxial line. The GND line (14) and the feed line (16) are arranged outside the high frequency signal line (12).

Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.