An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.

A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

A transistor outline housing is provided that includes a header for an optoelectronic component. The header has electrical feedthroughs in the form of connection pins embedded in a potting compound. The header has a recess in which at least one of the connection pins in one of the feedthroughs extends out of the lower surface of the header.

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

An antenna apparatus includes a substrate including a first main side and a second main side arranged opposite thereto. The antenna apparatus further includes a first and a second fixing region arranged at the first main side. The antenna apparatus includes a ribbon connecting the first fixing region and the second fixing region, which is at least regionally spaced apart from the substrate. Furthermore, the antenna apparatus includes a metallization arranged at the second main side, which is arranged opposite to at least one of the first fixing region, the second fixing region and the ribbon.

A semiconductor light emitting apparatus includes: a stem part having a stem base, a lead terminal, and a metal member having a closed shape, the stem base having an inner portion having a first face, a second face and an opening extending in a first direction from the first face to the second face, and an outer portion surrounding the inner portion, the inner and outer portions being arranged along a reference plane intersecting the first direction, the lead terminal being supported in the opening, and the metal member being disposed on the outer portion so as to surround the inner portion and having a first portion supported by a top face of the outer portion, and a second portion extending outward with reference to an edge of the outer portion; a semiconductor optical element disposed on the inner portion; and a cap disposed on the metal member.

Semiconductor dies in a stack of semiconductor dies are interconnected using metal lines instead of bond wires or through silicon vias (TSVs). The semiconductor dies in the stack are arranged in a stairstep configuration such that a step corner is defined between a top surface of a first semiconductor die in the stack and a sidewall of a second semiconductor die in the stack. A step ramp is formed in the step corner. The step ramp defines a slope that extends between the top surface of the first semiconductor die and a top surface of the second semiconductor die. A metal line is formed over a bond pad associated with the first semiconductor die, the step ramp and a bond pad associated with the second semiconductor die.

A semiconductor package includes a flat plate-shaped terminal integrally formed with a housing portion for a semiconductor chip and a rod-shaped terminal pin that penetrates through a through-hole of the plate-shaped terminal. On a surface of the plate-shaped terminal, a resin guide portion for guiding the terminal pin to the through-hole of the plate-shaped terminal is provided. The resin guide portion is a portion of the housing portion and has a through-hole that is continuous with the through-hole of the plate-shaped terminal. During assembly of the semiconductor package, the terminal pin is inserted into the through-hole of the plate-shaped terminal, via the through-hole of the resin guide portion. A sidewall of the through-hole of the resin guide portion and a sidewall of the through-hole of the plate-shaped terminal have a same slope and form a single continuous surface; a border between the through-hole of the resin guide portion and the through-hole of the plate-shaped terminal is free of any step.

An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the conductive areas. An integrated circuit (IC) is carried by the substrate. Bond wires are coupled between the IC and respective ones of the conductive areas. An encapsulating material is over the IC and adjacent portions of the substrate. A conductive layer is on the encapsulating material, and at least one conductive body is coupled between the at least one edge conductive area and the conductive layer.