Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.

This disclosure relates to a mobile device with a transmission line for a radio frequency (RF) signal. The transmission line includes a bonding layer having a bonding surface, a barrier layer proximate the bonding layer, a diffusion barrier layer proximate the barrier layer, and a conductive layer proximate the diffusion barrier layer. The barrier layer and the diffusion barrier layer are configured to prevent conductive material from the conductive layer from entering the bonding layer. The diffusion barrier layer has a thickness sufficiently small such that a radio frequency signal is allowed to penetrate the diffusion barrier layer and propagate in the conductive layer.

This disclosure relates to a mobile device with a transmission line for a radio frequency (RF) signal. The transmission line includes a bonding layer having a bonding surface, a barrier layer proximate the bonding layer, a diffusion barrier layer proximate the barrier layer, and a conductive layer proximate the diffusion barrier layer. The barrier layer and the diffusion barrier layer are configured to prevent conductive material from the conductive layer from entering the bonding layer. The diffusion barrier layer has a thickness sufficiently small such that a radio frequency signal is allowed to penetrate the diffusion barrier layer and propagate in the conductive layer.

Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip. The die pad includes a wire-bonding region to which the wire is connected and a through hole penetrating through the die pad in a thickness direction. The wire-bonding region is covered by a metal film partially covering the die pad. The through hole is formed at a position overlapping the metal film. The encapsulation body includes a first portion formed over the die pad, a second portion formed under the die pad, and a third portion buried in the through hole of the die pad, wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion.