A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.

A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.

A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.

Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.