An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening.

An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening.