A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips.

A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips.

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.