A connection member for connecting an electronic chip, wherein the connection member comprises a bulk body, and a coating at least partially coating the bulk body and comprising a material having higher electric and higher thermal conductivity than the bulk body, wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at at least a part of the connection member.

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

A bonding tool includes a wedge tool that presses a bonding wire against a principal plane of a structure such as an electrode to which the bonding wire is to be bonded. A groove formed in an end portion of a wedge tool body of the wedge tool is inclined along a longitudinal direction of the bonding wire so that a heel side of the groove is closer to the principal plane of the structure than a toe side of the groove. As a result, the wedge tool is inclined at a tilt angle and the bonding wire fits the groove in the end portion of the wedge tool body along the longitudinal direction of the bonding wire. Thus, a corner portion of the wedge tool does not contact the electrode.

A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

A semiconductor device includes a BGA package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

A semiconductor device includes a BGA package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.