A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode.

Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.

Methods related to plating a through-wafer via of a gallium arsenide integrated circuit are disclosed. For example, to improve copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. Other methods related to metallizing a through wafer via in gallium arsenide integrated circuits are disclosed. Such methods can include copper plating a through wafer via of a gallium arsenide integrated circuit.

Methods related to plating a through-wafer via of a gallium arsenide integrated circuit are disclosed. For example, to improve copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. Other methods related to metallizing a through wafer via in gallium arsenide integrated circuits are disclosed. Such methods can include copper plating a through wafer via of a gallium arsenide integrated circuit.

A method comprises heating a first electrically conductive layer that is to be electrically contacted, and that is arranged on a first element, and pressing a first end of a bonding wire on the first electrically conductive layer by exerting pressure to the first end of the bonding wire, and further by exposing the first end of the bonding wire to ultrasonic energy, thereby deforming the first end of the bonding wire and creating a permanent substance-to-substance bond between the first end of the bonding wire and the first electrically conductive layer. The bonding wire either comprises a rounded cross section with a diameter of at least 125 m or a rectangular cross section with a first width of at least 500 m and a first height of at least 50 m.

An IC includes a bare die and a multiplexed pin. The multiplexed pin is electrically connected to first and second switch circuits, the first and second switch circuits are respectively connected to first and second circuit modules disposed on the bare die and control a connection between the first and second circuit modules and the multiplexed pin, the first switch circuit is connected to a first die pad by a metal layer trace within the bare die, the second switch circuit is connected to a second die pad by a metal layer trace within the bare die, and the first and second die pads are connected to the multiplexed pin through a bond wire respectively. The bare die with a larger number of die pads can be packaged into an IC package with a smaller number of chip pins.

A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.

A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.