A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.