Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O.sub.2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O.sub.2 or chloride (Cl.sub.2) while supplying nitrogen (N.sub.2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.

Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

A plasma processing apparatus 1 that performs, on a wafer 16 in which a multilayer film in which an insulating film and a film to be processed containing a metal are alternately laminated is formed on a substrate, plasma etching of the film to be processed, includes: a processing chamber 10 which is disposed inside a vacuum container; a sample stage 14 which is disposed inside the processing chamber and on which the wafer is placed; a detection unit 28 which detects reflected light obtained by the wafer reflecting light emitted to the wafer; a control unit 40 which controls plasma processing on the wafer; and an end point determination unit 30 which determines an etching end point of the film to be processed based on a change in an amplitude of vibration in a wavelength direction of a light spectrum of the reflected light, and the control unit receives determination of the end point made by the end point determination unit and stops the plasma processing on the wafer.

Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a plurality of apertures. The systems may include a plurality of lid stacks. The systems may include a plurality of substrate supports. The systems may include a plurality of peripheral valves. Each peripheral valve may be disposed in one of the processing regions. Each peripheral valve may include a bottom plate coupled with the chamber body. The peripheral valve may include a bellow. The bellow may be coupled with the bottom plate. The peripheral valve may include a sealing ring having a body defining a central aperture. A bottom surface of the body may be coupled with the bellow. The body may define a recess having a diameter greater than that of a support plate of a substrate support.

The present invention provides a GaN/two-dimensional AlN heterojunction rectifier on a silicon substrate and a preparation method therefor and belongs to the field of rectifiers. The rectifier comprises a silicon substrate, a GaN buffer layer, a carbon-doped semi-insulating GaN layer, a two-dimensional AlN layer, a non-doped GaN layer, a non-doped InGaN layer and a SiN.sub.x passivation layer that are stacked in sequence. The rectifier further comprises a mesa isolation groove and a Schottky contact electrode that are arranged at one side. The mesa isolation groove is in contact with the non-doped GaN layer, the non-doped InGaN layer, the SiN.sub.x passivation layer and the Schottky contact electrode. The Schottky contact electrode is in contact with the mesa isolation groove and the non-doped GaN layer. The thickness of the two-dimensional AlN layer is only several atomic layers, thus the received stress and polarization intensity are greater than those of the AlGaN layer.

A method for cleaning contacts on a substrate incorporates ion control to selectively remove oxides. The method includes exposing the substrate to ions of an inert gas, supplying a first RF frequency of a first bias power supply to a substrate support, supplying a second RF frequency of a second bias power supply to a substrate support, and adjusting a first power level of the first RF frequency and a second power level of the second RF frequency to selectively remove oxide from at least one contact on the substrate while inhibiting sputtering of polymer material wherein the oxide removal is selective over removal of polymer material surrounding the at least one contact.