In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.

A semiconductor package includes a first substrate having a first surface and including a first electrode, a first bump pad located on the first surface of the first substrate and connected to the first electrode, a second substrate having a second surface facing the first surface of the first substrate and including a second electrode, a second bump pad and neighboring second bump pads on the second surface of the second substrate, and a bump structure. The second bump pad has a recess structure. That is recessed from a side surface of the second bump pad toward a center thereof. The second bump pad may be connected to the second electrode. A bump structure may contact the first bump pad and the second bump pad. The bump structure may have a portion protruding through the recess structure. The neighboring second bump pads may neighbor the second bump pad and include recess structures oriented in different directions.

The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.

A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.