A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer.

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

Photonic devices include a photonic assembly and a substrate coupled to the photonic assembly. The photonic assembly includes a photonic die and an optical device coupled to the photonic die with an adhesive to form an optical connection between the optical device and the photonic die. The photonic assembly is coupled to the photonic assembly by reflowing a plurality of solder connections at temperature that is less than a cure temperature of the adhesive.

Disclosed herein are embodiments of lead-free (Pb-free) or lead-bearing solder column devices that can include an inner core, an outer sleeve surrounding a portion of the inner core, at least one space along a length of the outer sleeve, and a second layer including a solder material coupled with a portion of the inner core within the at least one space. The inner core can be configured to support the solder column so as to prevent a collapse of the solder column at temperatures above a liquidus temperature of the outer sleeve's solder material and the second layer's solder material. The column serves as a heat-sink to conduct excessive heat away from a heat generating semiconductor chip. Moreover, the compliant solder column absorbs strain and mechanical stress caused by a difference in the coefficient of thermal expansion (CTE) connecting the semiconductor chip to a printed circuit board (PCB).

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Provided is a semiconductor element mounting structure, including: a semiconductor element including an element electrode, and a substrate including a substrate electrode that is provided on a surface facing the semiconductor element at a position facing the element electrode, the semiconductor element and the substrate being connected via the element electrode and the substrate electrode, in which: one of the element electrode or the substrate electrode is a first protruding electrode including a solder layer at a tip portion thereof, the other of the element electrode or the substrate electrode is a first electrode pad including one or more metal protrusions on a surface thereof, the one or more metal protrusions of the first electrode pad extend into the solder layer of the first protruding electrode, and a bottom area of each of the one or more metal protrusions of the first electrode pad is 70% or less with respect to an area of the first electrode pad, or 75% or less with respect to a maximum cross-sectional area of the solder layer of the first protruding electrode.

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.