A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Methods for forming a metal carbide liner in features formed in a substrate surface are described. Each of the features extends a distance into the substrate from the substrate surface and have a bottom and at least one sidewall. The methods include depositing a metal carbide liner in the feature of the substrate surface with a plurality of high-frequency ratio-frequency (HFRF) pulses. Semiconductor devices with the metal carbide liner and methods for filling gaps using the metal carbide liner are also described.

A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.

In order to implement a plasma etching method for improving a tapered shape, a plasma processing apparatus includes: a processing chamber in which a sample is subjected to plasma processing; a first radio frequency power source that supplies radio frequency power for generating a plasma; a sample stage on which the sample is placed; a second radio frequency power source that supplies radio frequency power to the sample stage; and a control unit that controls the first radio frequency power source and the second radio frequency power source so as to etch a stacked film formed by alternately stacking a silicon oxide film and a polycrystalline silicon, or a stacked film formed by alternately stacking a silicon oxide film and a silicon nitride film, by using a plasma generated by a mixed gas of a hydrogen bromide gas, a hydrofluorocarbon gas and a nitrogen element-containing gas.

An apparatus and method for etching a material layer with a cyclic etching and deposition process. The method for etching a material layer on a substrate includes: (a) etching at least a portion of a material layer (302) on a substrate (101) in an etch chamber (100) to form an open feature (360) having a bottom surface (312) and sidewalls in the material layer (302); (b) forming a protection layer (314) on the sidewalls and the bottom surface (312) of the open feature (360) from a protection layer (314) gas mixture comprising at least one carbon-fluorine containing gas; (c) selectively removing the protection layer (314) formed on the bottom surface (312) of the open feature (360) from a bottom surface (312) open gas mixture comprising the carbon-fluorine containing gas; and (d) continuingly etching the material layer (302) from the bottom surface (312) of the open feature (360) until a desired depth of the open feature (360) is reached.

A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.