Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

An etching method enables plasma etching of a silicon-containing film with reduced lateral etching. The etching method includes providing a substrate in a chamber included in a plasma processing apparatus. The substrate includes a silicon-containing film. The etching method further includes setting a flow rate proportion of a phosphorus-containing gas with respect to a total flow rate of the process gas so as to establish a predetermined ratio of an etching rate of an alternate stack of a silicon oxide film and a silicon nitride film to an etching rate of the silicon oxide film.

An etching method includes: (a) providing a substrate that contains silicon, on a support; (b) etching the substrate with plasma generated from a first gas that includes a fluorine-containing gas, to form an etching shape having a bottom; (c) generating plasma from a second gas that includes a hydrogen fluoride (HF) gas, to selectively form a condensed or solidified layer of HF at the bottom of the etching shape; and (d) etching the bottom with the plasma generated from the second gas, by supplying a bias power to the support. During (c) and (d), a temperature of the substrate is maintained to be 0° C. or lower.

A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

A technique protects a mask in plasma etching of a silicon-containing film. An etching method includes providing a substrate in a chamber included in a plasma processing apparatus. The substrate includes a silicon-containing film and a mask. The mask contains carbon. The etching method further includes etching the silicon-containing film with a chemical species in plasma generated from a process gas in the chamber. The process gas contains a halogen and phosphorus. The etching includes forming a carbon-phosphorus bond on a surface of the mask.

The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

A plasma processing apparatus includes a plasma chamber that accommodates a substrate having a film including a side wall surface and a bottom surface that define an opening; and a controller that controls a process on the substrate in the plasma chamber. The controller includes a sequencer that performs a sequence including forming a precursor layer on the opening of the film; and generating a plasma to form a protective film on the side wall surface of the opening of the film from the precursor layer and to etch the bottom surface of the opening of the film. The controller simultaneously forms the protective film on the side wall surface of the opening of the film and etches the bottom surface of the opening of the film.

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.