The present application provides an electrostatic discharge guard structure for photonic platform based photodiode systems. In particular this application provides a photodiode assembly comprising: a photodiode (such as a Si or SiGe photodiode); a waveguide (such as a silicon waveguide); and a guard structure, wherein the guard structure comprises a diode, extends about all or substantially all of the periphery of the Si or SiGe photodiode and allows propagation of light from the silicon waveguide into the Si or SiGe photodiode.

To provide an electronic component having a protective film formed with good uniformity, over the entire surface thereof. The electronic component has a protective film formed over the entire surface thereof, and the electronic component has elements and wirings formed on a base body. The protective film is formed by a CVD method, over an entire surface of the electronic component, by: arranging an electrode in a chamber; grounding one side of the chamber and the electrode; accommodating the electronic component in the chamber; supplying a raw material gas to the chamber; rotating or swinging the chamber and thereby moving the electronic component in the chamber; supplying high-frequency power to the other side of the chamber and the electrode; and generating a raw-material-gas-based plasma between the electrode and the chamber.

A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.

A solar cell apparatus 100 and a method for forming said solar cell apparatus 100, comprising a substrate 101, a n-type transparent conductive oxide (TCO) layer 102 deposited atop said substrate 101, a p-i-n structure 200 that includes a p-type layer 103, an i-type layer 104, a n-type layer 105, a metal back layer 106 deposited atop said n-type layer 105 of the p-i-n structure 200. The n-type layer 105 comprises n-type donors 115 including phosphorus atoms. The n-type donors 115 include oxygen atoms at an atomic concentration comprised between 5% and 25% of the overall atomic composition of the n-type layer 105.

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

A solar cell panel includes a first solar cell and a second solar cell; and a plurality of leads connecting the first solar cell and the second solar cell. Each of the first solar cell and the second solar cell includes: a first electrode including a plurality of finger lines in a first direction and a plurality of first bus bars in a second direction crossing the first direction; and a second electrode including a plurality of second bus bars in the second direction. The plurality of leads have a diameter or width of 100 to 500 μm, and include 6 or more leads arranged at one surface side of the first or second solar cell. The plurality of leads are connected to the plurality of first bus bars of the first solar cell and the plurality of second bus bars of the second solar cell by a solder layer, respectively.

In manufacturing an image sensor for FPD having an oxide semiconductor TFT as a switching element, a large amount of hydrogen contained in raw gas is diffused in the oxide semiconductor at the time of forming a-Si photo diode (PD) which is a photoelectric conversion element, causing significant variation in the characteristic of TFT which may thereby not operate. In an image sensor in which an oxide semiconductor TFT and a-Si PD are formed on a substrate in this order, a gas barrier film is disposed between the oxide semiconductor TFT and the PD, and the drain terminal (drain metal) of the oxide semiconductor TFT is connected to one terminal (lower electrode) of the PD via connection wiring (bridge wiring) formed on a protective film arranged over the PD.

A rear contact heterojunction solar cell and a fabricating method. The solar cell comprises a silicon substrate having a passivating layer and an intrinsic amorphous silicon layer. At a back side of the intrinsic amorphous silicon layer, an emitter layer and a base layer are provided. Interposed between these emitter and base layers is a separation layer comprising an electrically insulating material. This separation layer as well as the base layer and emitter layer may be generated by vapor deposition. Due to such processing, adjacent regions of the emitter layer and the separating layer and adjacent regions of the base layer and the separating layer partially laterally overlap in overlapping areas in such a way that at least a part of the separating layer is located closer to the substrate than an overlapping portion of the respective one of the emitter layer and the base layer.

A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.