To improve the photoelectric conversion efficiency of a p-n junction solar cell by adding a minimum element thereto to widen the absorption wavelength range thereof.

Solving Means

Nano particles obtained by terminating surfaces of silicon nanoparticles having a diameter of not more than 5 nm with molecules of hydrocarbon are disposed on the outermost surface of a semiconductor forming a p-n junction solar cell that uses silicon or the like. These silicon nanoparticles absorb energy of ultraviolet light, and the energy is transferred to the p-n junction solar cell. In this way, a solar cell composite that efficiently utilizes light ranging to the ultraviolet region without requiring the use of additional wiring or the like is obtained.

Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

A method of forming a micro-structure involves forming a multi-layered structure including i) an oxidizable material layer on a substrate and ii) another oxidizable material layer on the oxidizable material layer. The oxidizable material layer is formed of an oxidizable material having an expansion coefficient, during oxidation, that is more than 1. The method further involves forming a template, including a plurality of pores, from the other oxidizable material layer, and growing a nano-pillar inside each pore. The nano-pillar has a predefined length that terminates at an end. A portion of the template is selectively removed to form a substantially even plane that is oriented in a position opposed to the substrate. A material is deposited on at least a portion of the plane to form a film layer thereon, and the remaining portion of the template is selectively removed to expose the nano-pillars.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Provided is a nanowire manufacturing substrate, comprising a grid base layer on a substrate and a grid pattern formed by patterning the grid base layer, the grid pattern being disposed to produce a nanowire on a surface thereof. According to the present invention, the width and height of the nanowire can be adjusted by controlling the wet-etching process time period, and the nanowire can be manufactured at a room temperature at low cost, the nanowire can be mass-manufactured and the nanowire with regularity can be manufactured even in case of mass production.

In an embodiment of the disclosure, a structure is provided which comprises a silicon substrate and a plurality of necklaces of silicon nanowires which are in direct physical contact with a surface of the silicon substrate, wherein the necklaces cover an area of the silicon substrate.