One illustrative method embodiment includes: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.

Provided is an electronic component package for electromagnetic interference shielding. The electronic component package for electromagnetic interference shielding according to an embodiment of the present invention comprises a substrate where electronic components are mounted, a molding member formed on the substrate and the electronic components, a magnetic layer formed on the molding member, and a conductive layer formed on the magnetic layer. Electromagnetic waves generated from the electronic components embeded in the molding member are absorbed in the magnetic layer to thus prevent or reduce harmful influence on other electronic components mounted in adjacent places. In addition, harmful electromagnetic waves generated from the outside may be shielded due to the conductive layer formed on the magnetic layer, thereby protecting electronic components embeded in the molding member from being influenced by the electromagnetic waves.

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

In implementations of device component exposure protection, a computing device includes device components enclosed within a housing. The device components are assembled within the housing and enclosed within the housing upon completion of assembly of the computing device. The computing device further includes a protective material contained within the housing, which fills void spaces around the device components. The protective material prevents exposure of the device components to external matter that the computing device is exposed to upon completion of the assembly.

The present invention provides a piezoelectric quartz crystal resonator. The piezoelectric quartz crystal resonator comprises a circuit board, a quartz crystal resonator and a thermistor, wherein the thermistor is configured to detect a temperature of the quartz crystal resonator, the thermistor and the quartz crystal resonator are arranged on the circuit board and interconnected with each other via electric wires arranged on the circuit board; the thermistor and the quartz crystal resonator are sealed independently from each other by thermoplastic material, and the thermoplastic material sealing the thermistor is in contact with the thermoplastic material sealing the quartz crystal resonator.

A connector arrangement includes a plug nose body; a printed circuit board positioned within a cavity of the plug nose body; and a plug cover that mounts to the plug nose body to enclose the printed circuit board within the cavity. The printed circuit board includes a storage device configured to store information pertaining to the electrical segment of communications media. The plug cover defines a plurality of slotted openings through which the second contacts are exposed. A connector assembly includes a jack module and a media reading interface configured to receive the plug. A patch panel includes multiple jack modules and multiple media reading interfaces.

A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a step of preparing a sheet having thermosetting property; a disposing step of disposing the sheet on the mounting member so as to face the second circuit members; and a sealing step of pressing the sheet against the first circuit member and heating the sheet, to seal the second circuit members and to cure the sheet, wherein the second circuit members include a reference member, and a first adjacent member and a second adjacent member each adjacent to the reference member, a separation distance D1 between the reference member and the first adjacent member is different from a separation distance D2 between the reference member and the second adjacent member, at least one of the plurality of the second circuit members is a hollow member to be provided with a space from the first circuit member, and in the sealing step, the plurality of the second circuit members are sealed so as to maintain the space.

A method of manufacturing a sealed circuit card assembly includes disposing a circuit card assembly within a volume defined by a housing and at least partially filling the volume with a curable liquid such that the curable liquid encapsulates at least a circuit card. The method may also include curing the curable liquid to form a potted circuit card assembly and, after at least partially filling the volume with the curable liquid and after curing the curable liquid, vacuum impregnating the potted circuit card assembly with a sealant to seal any exposed interfaces or cracks to form the sealed circuit card assembly. Accordingly, the sealed circuit card assembly may include a first cured material encapsulating the circuit card of the circuit card assembly and a second cured material disposed within, for example, a porosity of the first cured material.

A substrate support for control of a temperature of a semiconductor substrate supported thereon during plasma processing of the semiconductor substrate includes a temperature-controlled base having a top surface, a metal plate, and a film heater. The film heater is a thin and flexible polyimide heater film with a plurality of independently controlled resistive heating elements thermally coupled to an underside of the metal plate. The film heater is electrically insulated from the metal plate. A first layer of adhesive bonds the metal plate and the film heater to the top surface of the temperature-controlled base. A layer of dielectric material is bonded to a top surface of the metal plate with a second layer of adhesive. The layer of dielectric material forms an electrostatic clamping mechanism for supporting the semiconductor substrate.

A method for fabricating a piezoelectric quartz crystal resonator is disclosed, which comprises: arranging a plurality of design units on a circuit board, wherein each design unit includes a quartz crystal resonator and a thermistor, and a division clearance is preset between every two adjacent design units; in each design unit, arranging at least one extension welding pad and at least one resonator welding pad; arranging at least one thermistor welding pad corresponding to the thermistor at the circuit board; welding the quartz crystal resonator and the thermistor onto their corresponding welding pads respectively; using thermoplastic material to seal the welded quartz crystal resonator and thermistor; dividing the circuit board processed by the thermoplastic material according to the design units.