A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A device includes a plurality of first pads in a package substrate, wherein at least one first pad is of a first elongated shape, a plurality of vias in a dielectric layer and over the plurality of first pads, and a plurality of second pads over the package substrate, wherein at least one second pad is of a second elongated shape, and wherein the plurality of second pads is over a top surface of the dielectric layer and placed in a first region, a second region, a third region and a fourth region, and wherein second pads in two contiguous regions are oriented in two different directions.

A method of interconnecting a conductor and a hermetic feedthrough of an implantable medical device includes welding a lead to a pad on a feedthrough. The feedthrough includes a ceramic insulator and a via hermetically bonded to the insulator. The via includes platinum. The pad is bonded to the insulator and electrically connected to the via, includes platinum, and has a thickness of at least 50 m. The lead includes at least one of niobium, platinum, titanium, tantalum, palladium, gold, nickel, tungsten, and oxides and alloys thereof.

A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.