A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.

A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

A wirelessly enabled content delivery apparatus includes a surface. The surface has a front side and a back side. An electronics board has a through hole. A conductive touch pad layer is placed between the back side of the surface and the electronics board. The electronics board further includes a conductive element. The conductive element passes through the through hole. A wireless data module is part of a wireless data system. The wireless data system is attached to the electronics board and the wireless data module is electrically connected to a first end of the conductive element. The electronics board is coupled to the back side of the surface and is aligned so that a second end of the conductive element is in electrical contact with the touch pad layer. The wireless data module is configured to receive a control input when a user touches the front side of the surface in the vicinity of the touch pad wherein the touch pad and the conductive element are part of the control circuit which controls the wireless data system. A method includes creating a touch pad from a conductive layer of material. A through hole of an electronics board is positioned to align with the touch pad. A spring pin is inserted into the through hole of the electronics board. The electronics board contains a wireless data module, and a first end of the spring pin is electrically connected to the wireless data module. The touch pad is located onto a back side of a surface. The electronics board is attached to the back side of the surface wherein a second end of the spring pin makes electrical contact with the touch pad such that when a user touches a front side of the surface a control signal is sent to the wireless data module.

An interconnection substrate includes: a substrate having a first surface and a second surface opposite the first surface; and a transmission line including two parallel through-hole interconnections that are exposed to the first and second surfaces and are formed inside the substrate. Also, at least one of the two through-hole interconnections includes a narrow portion having a smaller diameter than a diameter of the through-hole interconnection in the first surface and a diameter of the through-hole interconnection in the second surface.

A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-metal-layer contains metal different from second metal.

A method making a three-dimensional inductor, the method including: forming a plurality of vias in a substrate or a molding compound, wherein the vias are arranged with spacings among them; forming a metal layer having interconnects, wherein the interconnects of the metal layer connect the plurality of vias on one end of the vias; forming a plurality of wires to connect the plurality of vias on the other end of the vias to form the 3D inductor; and tuning one or more of the plurality of wires to adjust a physical configuration and inductance value of the 3D inductor.

In one embodiment, a printed circuit board (PCB) assembly includes a PCB, the PCB being arranged to define a through-hole therein, the through-hole having a surface, wherein the PCB includes a top surface and a bottom surface. The PCB assembly also includes a slug arrangement and a surface mount component. The slug arrangement is formed from an electrically and thermally conductive material and includes at least a first portion and a second portion. At least a part of the first portion is positioned in the through-hole, and the second portion is coupled to the bottom surface. The surface mount component is positioned over the through-hole and the top surface, and has a first surface configured to contact the first portion.

A method for repairing a fine line is provided. Nano metal particles are filled in a defect of a circuit board. The nano metal particles in the defect are irradiated by a laser, or heated, such that the nano metal particles in the defect are metallurgically bonded to an original line of the circuit board. A surface of the circuit board is cleaned to remove residual nano metal particles on parts of the circuit board where metallurgical bonding is not performed, thereby completing line repairing of the circuit board.