A method of attaching a MEMS die to a base includes selecting an attachment material (x), determining a maximum acceptable change in pressure due to mounting stress (dPtarget) transmitted to a MEMS die, determining a worst-case pressure difference transfer function of the attachment material (x) over a thickness (h) variation of the attachment material (x) using the equation: dPmax.sub.x=h*B.sub.x+C.sub.x, wherein B=pressure variation/thickness (h), and C=pressure variation, substituting dPtarget for dPmax.sub.x in the pressure difference transfer function and solving the equation for h, wherein h=(dPtargetC.sub.x)/B.sub.x, and attaching the MEMS die to a base using the selected attachment material (x) having at least the calculated thickness (h).

A method includes fusion bonding a first side of a MEMS wafer to a second side of a first handle wafer. A TSV is formed from a first side of the first handle wafer to the second side of the first handle wafer and into the first MEMS wafer. A dielectric layer is formed on the first side of the first handle wafer. A tungsten via is formed in the dielectric layer. Electrodes are formed on the dielectric layer. A second MEMS wafer is eutecticly bonded with a first eutectic bond to the electrodes, wherein the TSV electrically connects the first MEMS wafer to the second MEMS wafer. Standoffs are formed on a second side of the first MEMS wafer. A CMOS wafer is eutecticly bonded with a second eutectic bond to the standoffs, wherein the second eutectic bond includes different materials than the first eutectic bond.

Nanopore flow cells and methods of manufacturing thereof are provided herein. In one embodiment a method of forming a flow cell includes forming a multi-layer stack on a first substrate, e.g., a monocrystalline silicon substrate, before transferring the multi-layer stack to a second substrate, e.g., a glass substrate. Here, the multi-layer stack features a membrane layer, having a first opening formed therethrough, where the membrane layer is disposed on the first substrate, and a material layer is disposed on the membrane layer. The method further includes patterning the second substrate to form a second opening therein and bonding the patterned surface of the second substrate to a surface of the multi-layer stack. The method further includes thinning the first substrate and thinning the second substrate. Here, the second substrate is thinned to where the second opening is disposed therethrough. The method further includes removing the thinned first substrate and at least portions of the material layer to expose opposite surfaces of the membrane layer.

Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. Standoffs are formed on a second side of the device wafer. A first hardmask is deposited on the second side. A second hardmask is deposited on the first hardmask. A surface of the second hardmask is planarized. A photoresist is deposited on the second hardmask, wherein the photoresist includes a MEMS device pattern. The MEMS device pattern is etched into the second hardmask. The MEMS device pattern is etched into the first hardmask, wherein the etching stops before reaching the device wafer. The photoresist and the second hardmask are removed. The MEMS device pattern is further etched into the first hardmask, wherein the further etching reaches the device wafer. The MEMS device pattern is etched into the device wafer. The first hardmask is removed.

The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

A microelectromechanical device having a first substrate of semiconductor material and a second substrate of semiconductor material having a bonding recess delimited by projecting portions, monolithic therewith. The bonding recess forms a closed cavity with the first substrate. A bonding structure is arranged within the closed cavity and is bonded to the first and second substrates. A microelectromechanical structure is formed in a substrate chosen between the first and second substrates. The device is manufactured by forming the bonding recess in a first wafer; depositing a bonding mass in the bonding recess, the bonding mass having a greater depth than the bonding recess; and bonding the two wafers.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Reversible (relatively weak) anodic bonds permit glass and silicon components to be separated without damaging the components so that they can be reused. To this end, chamfered glass with high aluminum content can be used during the original anodic bonding. Anodic bonding is terminated after complete intimate contact is achieved and while the bond is reversible. The high aluminum content impedes further bond strengthening so that the bond does not become non-reversible via contact bonding. The chamfer provides access near the glass-silicon interface for prying the glass off the silicon to effect debonding without damaging the glass or the silicon. Accordingly, the glass, the silicon, or both may be rebounded (rather than being wastefully disposed).

This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.