The invention relates to a method for cutting off at least one portion (4), in particular a wafer, from a solid body (2). The method comprises at least the following steps: modifying the crystal lattice of the solid body (2) by means of a modifier (18), wherein a number of modifications (19) are produced to form a nonplanar, in particular convex, detachment region (8) in the interior of the solid body, wherein the modifications (19) are produced in accordance with predetermined parameters, wherein the predetermined parameters describe a relationship between a deformation of the portion (4) and a defined further treatment of the portion (4), detaching the portion (4) from the solid body (2).

A cover window includes a plastic layer and a first hard coating layer disposed on an upper surface of the plastic layer. An edge of the cover window includes a vertical side part perpendicular to the upper surface of the plastic layer. A first inclination part is connected to the vertical side part and is inclined with respect to the vertical side part. The vertical side part and the first inclination part include a mechanical processing trace. An edge of the first hard coating layer adjacent to the first inclination part includes a laser processing trace.

A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

A mask-integrated surface protective tape, containing: a substrate film; a temporary-adhesive layer provided on the substrate film; and a mask material layer provided on the temporary-adhesive layer; wherein the mask material layer and the temporary-adhesive layer each contain a (meth)acrylic copolymer; and wherein the mask-integrated surface protective tape is used for a method of producing a semiconductor chip utilizing a plasma-dicing.

This paste composition includes silver particles (A), a thermosetting resin (B), a curing agent (C), and a solvent (D). A shrinkage rate after curing of the paste composition is 15% or less.

An optical device includes a plurality of laser light sources, an output module having an optical modulator, and a time divider that is disposed between the plurality of laser light sources and the output module and that is configured to divide laser beams emitted from the plurality of laser light sources in time.

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

A stage for cutting a substrate includes: a body member; a plurality of first discharging members, each including a first suction portion in the body member and a first partition wall portion connected to the first suction portion and protruding from a top surface of the body member, each of the first discharging members defining a first space connected to an outside; a plurality of second discharging members, each including a second suction portion in the body member and a second partition wall portion connected to the second suction portion and protruding from the top surface of the body member, each of the second discharging members defining a second space connected to the outside; a plurality of connecting pipes each connected to the first partition wall portion and the second partition wall portion; and a plurality of supply pipes connected to the connecting pipes.

In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.

Embodiments of the present disclosure include method for sequentially mounting multiple semiconductor devices onto a substrate having a composite metal structure on both the semiconductor devices and the substrate for improved process tolerance and reduced device distances without thermal interference. The mounting process causes “selective” intermixing between the metal layers on the devices and the substrate and increases the melting point of the resulting alloy materials.