A carrier for a double-side polishing apparatus configured to double-side polish providing a semiconductor silicon wafer. The carrier being disposed between upper and lower turn tables have a polishing pad attached, and includes a holding hole formed to hold the semiconductor silicon wafer between the upper and lower turn tables during polishing. The carrier for a double-side polishing apparatus is made of a resin. An average contact angle with pure water of front and back surfaces of the carrier, which come into contact with the polishing pads, is 45° or more and 60° or less, and a difference in average contact angles between the front surface and the back surface is 5° or less, which provides a carrier for a double-side polishing apparatus capable of enhancing the polishing rate for a semiconductor silicon wafer by using a resinous carrier; and a double-side polishing apparatus and method which employ the carrier.

A carrier for a double-side polishing apparatus configured to double-side polish providing a semiconductor silicon wafer. The carrier being disposed between upper and lower turn tables have a polishing pad attached, and includes a holding hole formed to hold the semiconductor silicon wafer between the upper and lower turn tables during polishing. The carrier for a double-side polishing apparatus is made of a resin. An average contact angle with pure water of front and back surfaces of the carrier, which come into contact with the polishing pads, is 45° or more and 60° or less, and a difference in average contact angles between the front surface and the back surface is 5° or less, which provides a carrier for a double-side polishing apparatus capable of enhancing the polishing rate for a semiconductor silicon wafer by using a resinous carrier; and a double-side polishing apparatus and method which employ the carrier.

A method of producing a carrier for use in a double-side polishing apparatus, the method including engaging an insert with a holding hole formed in a carrier body and sticking the insert to the holding hole, the carrier body being configured to be disposed between upper and lower turn tables to which polishing pads are attached of the double-side polishing apparatus, the holding hole being configured to hold a wafer during polishing, the insert being configured to contact an edge of the wafer to be held, the method including: performing a lapping process and a polishing process on the insert; engaging the insert subjected to the lapping process and the polishing process with the holding hole of the carrier body; and sticking and drying the engaged insert while applying a load to the insert in a direction perpendicular to main surfaces of the carrier body.

A method of producing a carrier for use in a double-side polishing apparatus, the method including engaging an insert with a holding hole formed in a carrier body and sticking the insert to the holding hole, the carrier body being configured to be disposed between upper and lower turn tables to which polishing pads are attached of the double-side polishing apparatus, the holding hole being configured to hold a wafer during polishing, the insert being configured to contact an edge of the wafer to be held, the method including: performing a lapping process and a polishing process on the insert; engaging the insert subjected to the lapping process and the polishing process with the holding hole of the carrier body; and sticking and drying the engaged insert while applying a load to the insert in a direction perpendicular to main surfaces of the carrier body.

A double-side polishing method including: disposing a wafer between a polishing pad attached to an upper surface of a lower turn table and a polishing pad attached to a lower surface of an upper turn table provided above the lower turn table; and polishing both sides of the wafer. An absolute value of a difference between a gap at inner circumferential portions of the two polishing pads and a gap at outer circumferential portions thereof is defined as a pad gap. The pad gap is larger when the both sides of the wafer are polished than when the two polishing pads are dressed. This provides a double-side polishing method that simultaneously achieves enhancement of quality level (processing precision) and extension of cloth life.

A double-side polishing method including: disposing a wafer between a polishing pad attached to an upper surface of a lower turn table and a polishing pad attached to a lower surface of an upper turn table provided above the lower turn table; and polishing both sides of the wafer. An absolute value of a difference between a gap at inner circumferential portions of the two polishing pads and a gap at outer circumferential portions thereof is defined as a pad gap. The pad gap is larger when the both sides of the wafer are polished than when the two polishing pads are dressed. This provides a double-side polishing method that simultaneously achieves enhancement of quality level (processing precision) and extension of cloth life.

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions.

A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0≤A+B≤2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.

A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0≤A+B≤2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.