An inkjet head chip identification circuit is disclosed and includes an identification circuit matching with a printer so that the printer provides an inkjet head chip with required information according to the matching result. The identification circuit includes plural memory units. The memory units arranged in an array structure and include a first transistor, a third transistor, a fuse or a combination thereof. By burning the elements in the array structure or not, a data signal of each memory unit is read. The first transistor is a MOSFET-Anti-Fuse. The third transistor is an EPROM. The first transistor, the third transistor and the fuse are formed on the same inkjet head chip.

A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.

A fluid ejection device includes a plurality of analog devices, and a storage element storing an authentication value based on electrical characteristics of a subset of the plurality of analog devices.

In an example, a method of managing a nozzle condition test on a printhead includes instructing a printhead to perform impedance measurements on a plurality of nozzles in a first set of nozzles. The method also includes retrieving from the printhead, an impedance measurement result corresponding with each nozzle, where each impedance measurement result indicates a nozzle condition of its corresponding nozzle.

In one example in accordance with the present disclosure a printhead with a number of EPROM cells is described. The printhead deposits fluid onto a print medium. The printhead also includes a number of EPROM cells. Each EPROM cell includes a substrate having a source and a drain disposed therein, a floating gate separated from the substrate by a first dielectric layer. The floating gate includes a multi-metal layer that is a metal etched layer. Each EPROM cell also includes a control gate separated from the multi-metal layer of the floating gate by a second dielectric layer.

A fluid ejection device includes a plurality of analog devices, and a storage element storing an authentication value including a plurality of bits, a first bit of the plurality of bits based on measured electrical characteristics of a first subset of the analog devices, and a second bit of the plurality of bits based on measured electrical characteristics of a second subset of the analog devices, the second subset different from the first subset.

A fluid ejection device includes a plurality of analog devices, and a storage element storing an authentication value including a plurality of bits, a first bit of the plurality of bits based on measured electrical characteristics of a first subset of the analog devices, and a second bit of the plurality of bits based on measured electrical characteristics of a second subset of the analog devices, the second subset different from the first subset.

A print head die includes a storage element. The print head die includes a plurality of analog devices. The storage element is to store an authentication value. The authentication value is generated based on comparisons of the measured electrical characteristics of at least some of the analog devices.

In an example, a method of managing a nozzle condition test on a printhead includes instructing a printhead to perform impedance measurements on a plurality of nozzles in a first set of nozzles. The method also includes retrieving from the printhead, an impedance measurement result corresponding with each nozzle, where each impedance measurement result indicates a nozzle condition of its corresponding nozzle.

A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.