Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a T-shape structure.

A semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include: a first trench isolation layer, a protective liner formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The protective liner separates the first trench isolation layer from the second trench isolation layer and the first trench isolation layer is more dense than the second trench isolation layer.

A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.

N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source/drain epitaxial layers on opposite sides of the first channel layer; forming second source/drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. The semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. The semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. The dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. The semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. The gate structure is divided into two portions by the cutting structure.

An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.