A method includes forming first, second, third, fourth, fifth, and sixth channel patterns on a semiconductor substrate; forming a first isolation wall interposing the first and second channel patterns, a second isolation wall interposing the third and fourth channel patterns, wherein the first isolation wall further continuously extends to interpose the fifth and sixth channel patterns; forming a first gate pattern extending across the first, second, third, and fourth channel patterns and the first and second isolation walls, and a second gate pattern extending across the fifth and sixth channel patterns and the first isolation wall from the top view, wherein the first, second, third, fourth, and sixth channel patterns respectively have first, second, third, fourth, and sixth dimensions in a lengthwise direction of the first gate pattern, and the sixth dimension is greater than the first, second, third, and fourth dimensions.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.

A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

A device structure includes a substrate, a fin structure disposed on the substrate and elongated in an X direction, a gate structure formed on the fin structure and elongated in a Y direction transverse to the X direction to terminate at two opposite ends, at least one dielectric portion connected to at least one of the two opposite ends of the gate structure, and having two sides that are opposite to each other in the X direction, and a pair of gate spacers which are spaced apart from each other in the X direction and are respectively disposed on two lateral sides of the gate structure, and which are elongated in the Y direction to cover the two sides of the dielectric portion, respectively. A method for manufacturing the device structure is also disclosed.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.