A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.

A method includes forming a fin structure including a first channel layer, a sacrificial layer, and a second channel layer over a substrate; forming a dummy gate structure across the fin structure; recessing the fin structure; epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer; forming first dielectric layers to cover the first source/drain epitaxial structures, respectively; epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer; removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and forming a metal gate structure in the gate trench. The second source/drain epitaxial structures are over the first dielectric layers, respectively.

A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.

A semiconductor device includes: a substrate; a fin protruding above the substrate; a gate structure over the fin; source/drain regions over the fin and on opposing sides of the gate structure; channel layers over the fin and between the source/drain regions, where the gate structure wraps around the channel layers; and isolation structures under the source/drain regions, where the isolation structures separate the source/drain regions from the fin, where each of the isolation structures includes a liner layer and a dielectric layer over the liner layer, where the dielectric layer has a plurality of sublayers.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.

Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.

A method for manufacturing a semiconductor structure includes: forming a channel portion on a fin portion; forming two source/drain portions on the fin portion and at two opposite sides of the channel portion, in which each of the two source/drain portions includes a first semiconductor material that is doped with dopant impurities; and forming two bottom portions each of which is disposed between the fin portion and a corresponding one of the two source/drain portions, in which each of the two bottom portions includes a second semiconductor material that is different from the first semiconductor material and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the fin portion.

Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a PFET source/drain (S/D). The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate, and an NFET S/D. The NFET S/D may include a silicon (Si)-based epi protruding into the BILD plane and a SiGe epi between the BILD and the Si-based.

Coupling qubits is provided. The method comprises embedding a tin atom in a silicon substrate and forming a number of quantum dot electrodes over the silicon substrate. The quantum dot electrodes draw an electron from an electron source into the silicon substrate and performing an electron-nuclear controlled-phase gate operation by: moving the electron adiabatically toward the tin atom to achieve a specified level of hyperfine interaction (HFI) between the electron and the nucleus of the tin atom to minimize the effect of noise; holding the electron at the distance of the specified HIFI for a specified duration of time to represent an on state; and moving the electron adiabatically away from the tin atom to lower the HFI below the specified level and represent an off state

According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.