A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.

A semiconductor device includes an active pattern including a lower pattern extending a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, the plurality of sheet patterns including an uppermost sheet pattern, a plurality of gate structures disposed to be spaced apart from each other in the first direction on the active pattern and including gate electrodes extending in a third direction and gate spacers on sidewalls of the gate electrodes and a source/drain pattern disposed between the gate structures adjacent to each other and including a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, wherein the semiconductor liner film covers a portion of an upper surface of an uppermost sheet pattern.

Related to the field of display panels, an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: the base substrate, the buffer layer, the active layer, the gate insulation layer, the gate, the interlayer insulation layer, the source, and the drain, which are stacked together. By using the gate insulation layer as a conductive mask of the active layer, and by adjusting the width of the gate and the width of the gate insulation layer, a width difference between the channel region and the gate is within the preset range, which reduces the problem of excessive width difference caused by the diffusion phenomenon of the channel region, and can at the same time meet the switching characteristics requirements of the thin film transistor and the definition requirements of the display panel.

A semiconductor device includes an insulating substrate, a silicon layer on the insulating substrate, a dopant layer on the silicon layer, a buried spacer on a side surface of the dopant layer, a channel pattern on the dopant layer, the channel pattern comprising a plurality of semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern on the buried spacer, the source/drain pattern connected to the channel pattern, a gate electrode on the channel pattern, the gate electrode comprising a plurality of inner electrodes between the semiconductor patterns, respectively, a lower power interconnection line in a lower portion of the insulating substrate, and a backside contact extending into the insulating substrate and the silicon layer to electrically connect the lower power interconnection line to the source/drain pattern. A side surface of the backside contact is in contact with the silicon layer and the buried spacer.

A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.