Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N.sup.+-type emitter region and p.sup.++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates. P.sup.+-type region covers an end portion on lower side of junction interface between n.sup.+-type emitter region and p.sup.++-type contact region. Formation of trench gate structure is such that n.sup.+-type emitter region is selectively formed at predetermined intervals in the first direction in the mesa portion by first ion implantation. P.sup.+-type region is formed less deeply than n.sup.+-type emitter region in the entire mesa portion by second ion implantation. The p.sup.++-type contact region is selectively formed inside the p+-type region by third ion implantation. N.sup.+-type emitter region and p.sup.++-type contact region are diffused and brought into contact.

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.

A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer. A recess is formed within the stack. The recess extends through the stack to the semiconductor substrate so that the recess at least partially overlaps with a surface of the collector region of the semiconductor substrate. The collector region extends from a main surface of the semiconductor substrate into the substrate material. The method further comprises generating a base structure at the collector region and in the recess. The base structure contacts and covers the collector region within the recess of the sacrificial layer. The method further comprises generating an emitter structure at the base structure. The emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer.

A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.