An IGBT includes a floating P well, and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour so that it has thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter, and through a first channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to a local bipolar transistor located at a thinner portion of the floating P type well. The transistor injects electrons down into the N drift layer. Other electrons pass farther through the floating N+ well, through the second channel region, and to an electron injector portion of the N drift layer. The extra electron injection afforded by the floating well structures reduces V.sub.CE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.

One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source region is formed by deposition, and a trench-shaped contact hole is used at the source region, in order to attain low contact resistance and small cell pitch. The present invention may also be implemented in an IGBT.

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.

The present application teaches, inter alia, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). Exemplary base drive circuits provide high-impedance drive to the base contact region on the side of the device instantaneously operating as the collector. (The B TRAN is controlled by applied voltage rather than applied current.) Current signals operate preferred implementations of drive circuits to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with low voltage drop (the transistor-ON state). In some preferred embodiments, self-synchronizing rectifier circuits provide adjustable low voltage for gate drive circuits. In some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while base current at that terminal is monitored, so no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain.