A manufacturing method of a semiconductor device includes: forming a mark on a surface of a semiconductor wafer, at least a part of the mark being disposed in a planned-peripheral region, the planned-peripheral region being located around a respective planned-element region where a semiconductor element is to be formed; forming the semiconductor element in the planned-element region using the mark; forming a film that extends across a range including the planned-element region or the planned-peripheral region in the surface so as to cover at least a part of the mark with the film, after forming the semiconductor element; and after forming the film, cutting the semiconductor wafer along a dicing region, the dicing region located around the planned-peripheral region.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and side surfaces; forming a mask pattern having an opening in which upper and side surfaces of the metal pattern therein being exposed; forming a barrier layer on the metal pattern exposed in the opening by a plating method; and forming a conducting layer on the barrier layer exposed in the opening.

In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

A semiconductor device comprises: a semiconductor device active region; an electrode shape controlling layer disposed on the semiconductor device active region, the electrode shape controlling layer containing aluminum, the content of aluminum being changed in a direction from bottom to up from the semiconductor device active region, an electrode region being disposed on the electrode shape controlling layer, a groove extended toward the semiconductor device active region and penetrating through the electrode shape controlling layer longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape corresponding to the content of aluminum in the electrode shape controlling layer; and an electrode disposed in the groove in the electrode region entirely or partially, the electrode having a shape matching with the shape of the groove, a bottom portion of the electrode being contacted with the semiconductor device active region.

Provided is a circuit board which includes a semiconductor substrate, a Zener diode, and a first vertical conductor and a second vertical conductor which configure a paired current path, wherein in the Zener diode, an N-type semiconductor region and a P-type semiconductor region being composed of the semiconductor substrate, with a PN junction extending in the thickness direction of the semiconductor substrate; and the first vertical conductor and the second vertical conductor penetrating the semiconductor substrate in the thickness direction, the first vertical conductor being brought into contact with the N-type semiconductor region, and the second vertical conductor being brought into contact with the P-type semiconductor region.

A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.