A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

A semiconductor device includes a drift region extending from a first surface into a semiconductor portion. A body region between two portions of the drift region forms a first pn junction with the drift region. A source region forms a second pn junction with the body region. The pn junctions include sections perpendicular to the first surface. Gate structures extend into the body regions and include a gate electrode. Field plate structures extend into the drift region and include a field electrode separated from the gate electrode. A gate shielding structure is configured to reduce a capacitive coupling between the gate structures and a backplate electrode directly adjoining a second surface.

The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.

A field effect transistor includes: a semiconductor substrate having a main surface; a plurality of source electrodes and a plurality of drain electrodes alternately disposed and ohmic-connected with the main surface of the semiconductor substrate; a plurality of gate electrodes Schottky-connected with the main surface of the semiconductor substrate and respectively disposed between the plurality of source electrodes and the plurality of drain electrodes; and a Schottky electrode Schottky-connected with the main surface of the semiconductor substrate, wherein each of the plurality of drain electrodes has first and second portions separated from each other, a sum of widths of the first and second portions of each drain electrode is smaller than a width of one source electrode, the Schottky electrode is disposed between the first portion and the second portion of the drain electrode.

A method of controlling a Casimir-effect device includes applying a voltage to a field-effect gate of the Casimir-effect device. The Casimir-effect device includes a conducting material and a semiconductor. The conducting material and semiconductor are separated by a gap to form the field-effect gate over at least a portion of the semiconductor facing the gap. The method further includes altering, in response to the applied voltage, a density of free charge carriers in the portion of the semiconductor facing the gap to control a nanoscale Casimir force between the conducting material and the portion of the semiconductor facing the gap.

Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.