More stable perpendicular magnetization orientation is attained, and switching of the magnetization orientation between an out-of-plane direction and an in-plane direction is enabled by voltage. A multiferroic laminated structure having ferroelectricity and ferromagnetism includes: a ferroelectric layer made of a ferroelectric substance having the ferroelectricity; a foundation layer composed mainly of a metal having a good lattice-matching property with the ferroelectric substance and laminated on a surface of the ferroelectric layer; an intermediate layer composed mainly of a non-magnetic substance and laminated on a surface of the foundation layer; and a ferromagnetic/non-magnetic multilayer film layer constituted by alternately laminating ferromagnetic layers and non-magnetic layers on a surface of the intermediate layer in at least three cycles, the ferromagnetic layers being composed mainly of a ferromagnetic substance, the non-magnetic layers being composed mainly of the non-magnetic substance.

A transistor and a manufacturing method of a transistor which prevents a decrease in mobility, prevents a decrease in a withstand voltage of the insulating layer, and prevents a short circuit between a gate electrode and a semiconductor layer due to curvature. A substrate having insulating properties, a source electrode and a drain electrode disposed in a surface direction of a main surface of the substrate by being separated from each other, a gate electrode disposed between the source electrode and the drain electrode in the surface direction of the substrate, a semiconductor layer disposed in contact with the source electrode and the drain electrode, and an insulating film disposed between the gate electrode and the semiconductor layer in a direction perpendicular to the main surface of the substrate are included, and a gap region is formed between the semiconductor layer and the insulating film.

The present invention provides a flexible substrate, a flexible display panel and a flexible display device. The flexible substrate includes an on-off element and an insulating layer, wherein a part of the insulating layer serves as a part of the on-off element, and the part of the insulating layer serving as a part of the on-off element is separated from rest part of the insulating layer. In the flexible substrate, the part of the insulating layer serving as a part of the on-off element is separated from the rest part of the insulating layer, such that cracks generated in the reset part of the insulating layer are unlikely to extend to the region where the on-off element is located, thus the poor contact or abnormal on-off phenomenon of the on-off element can be avoided.

The present invention relates to the field of manufacturing technologies of semiconductor power devices, and more particularly to a method for manufacturing a split-gate power device. In the method for manufacturing a split-gate power device according to the present invention, lateral etching is added to form lateral recesses of a control gate groove below a first insulating film in a process of forming the control gate groove by etching, and therefore, after a first conductive film is deposited, the first conductive film can be directly etched by using the first insulating film as a mask to form control gates. The technical process of the present invention is simplified, reliable and easy to control, and can greatly improve the yield of the split-gate power device. The present invention is particularly suitable for the manufacture of 25V-200V semiconductor power devices.

A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.

Provided are a semiconductor structure and a method of manufacturing the same. The method of manufacturing a semiconductor structure includes the following steps: a substrate and a stacked structure located on the substrate are provided, the stacked structure including first insulating layers and semiconductor layers alternately stacked along the vertical direction, and the stacked structure having a first region; parts of the stacked structure in the first region are etched to form multiple first trenches arranged at intervals and multiple first staircase regions located between the first trenches; second insulating layers are formed in the first trenches; the stacked structure in the multiple first staircase regions is etched along the vertical direction to form a first staircase structure; conductive layers are formed at the top of the first staircase structure; and the semiconductor layers under the conductive layers are removed.

Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure. The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (narrow mesa design rules, reliable planar process compatibility) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide SiC. Furthermore, the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process with minimum number of masks, with the potential of additionally applying enhancement layers and/or reverse conducting type of structures.

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.