The present invention provides a contact electrification effect-based back gate field-effect transistor. The back gate field-effect transistor includes: a conductive substrate; an insulating layer formed on a front face of the conductive substrate; a field-effect transistor assembly including: a channel layer, a drain and a source, and a gate; and a triboelectric nanogenerator assembly including: a static friction layer formed at a lower surface of the gate, a movable friction layer disposed opposite to the static friction layer and separated by a preset distance, and a second electro-conductive layer formed at an outside of the movable friction layer and being electrically connected to the source; wherein, the static friction layer and the movable friction layer are made of materials in different ratings in triboelectric series, and the static friction layer and the movable friction layer are switchable between a separated state and a contact state under the action of an external force.

An array substrate and its manufacturing method, and a touch display device are disclosed. A display area of the array substrate includes a plurality of thin film transistor (11), first transparent electrodes (12), second transparent electrodes (13) and a transparent insulation layer (16) that contacts the second transparent electrodes (13); the transparent insulation layer (16) is a conductor when a voltage applied thereon is larger than a predetermined voltage, and is an insulator when the voltage applied therein is less than the predetermined voltage. The second transparent electrodes (13) include first sub-electrodes (131) arranged into a plurality of rows in a first direction and insulated from each other, and second sub-electrodes (132) arranged into a plurality of rows in a second direction and insulated from each other, the first direction is intersected with the second direction. The problems such as noise, visual artifacts, insensitive to touch, or the like caused by unbalance of charges can be avoided.

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.

A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one LDMOS. The LDMOS includes a source, a drain and a gate. The drain is strip-shaped, the source and gate are cyclic structures, the inner circumference of the source is less than the outer circumference of the gate but is greater than the inner circumference of the gate, the inner ring of the source overlaps with the gate in all directions, and the drain is located inside the inner ring of the gate. Because the source and gate are configured as cyclic structures and the inner ring of the source overlaps with the gate in every direction, the layout structure can increase the current and reduce the area of LDMOS devices. Semiconductor devices manufactured based on the layout structure and electronic apparatuses including the semiconductor devices also have the above-described advantages.

A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

A semiconductor device includes: a substrate; a semiconductor stack including a first nitride semiconductor layer and a second nitride semiconductor layer formed above the substrate; a source electrode and a drain electrode formed above a lower surface of the semiconductor stack; a gate electrode; in plan view, a current-drift area; a non-current-drift area; and a collapse reducing electrode formed on the non-current-drift area in the second nitride semiconductor layer, the collapse reducing electrode being formed to have a substantially same potential as the gate electrode. In the semiconductor device, the collapse reducing electrode and the second nitride semiconductor layer have a junction surface functioning as an energy barrier having a rectifying effect in a forward direction from the collapse reducing electrode to the second nitride semiconductor layer.

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

A display panel structure includes a substrate, plural gate lines and data lines arranged on the substrate, plural pixel units, and plural dummy pixel units. The substrate has a display region and a peripheral region surrounding the display region. The gate lines and data lines are extended from the display region to the peripheral region. The pixel units are disposed at the display region. The dummy pixel units are disposed at the peripheral region, and include a first region, a second region, and a third region. The dummy pixel units of the first region and the second region are arranged along a first direction and a second direction, respectively. The dummy pixel units of the third region are arranged between the first and second regions. The dummy pixel units of the third region include one of the gate lines and one of the data lines.

The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.