A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.

A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.

A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.

A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.